The present-invention relates to an electric device and especially to a technique of repairing an error occurred in the electric device so that not only an output value of the electric device but also a circuit internal state value may not be changed and maintained with a wrong state.
The main factor of an occurrence of a soft error of an IC Integrated Circuit) is a particle radiation. The main source of this particle radiation is the radioactive decay from packaging material. Packaging material releases radioactive contaminants. Alpha radiators from these materials may pass through a semiconductor. A cosmic ray is another main source of the particle radiation. Although the cosmic ray doesn't nearly reach ground level, the cosmic ray may make powerful particle radiations like protons and Pions with considerable amount. Therefore, the level of the soft error induced by the particle radiation on the ground level may not be ignored. Energy transfer induced by ionization of two types of particle radiations in a semiconductor material generates electron-hole pairs, and an electric field in a transistor cause accumulation of electric charges in a circuit node. If the accumulated electric charges last during sufficient time, these may generates a transient voltage pulse flipping the digital value of the circuit node. The change induced from the soft error is generally called a SEU (Single-Event-Upset).
The SEU may occur in memory elements, sequential elements, and combinational elements, where the sequential elements among these are the most vulnerable to the SEU. Because of cross-coupled structure of a flip-flop and latch, an 1-bit flip by SET(Single-Event-Transient) on one node of a sequential element may induce a bit flip wrong value in other nodes, and then the wrong values in the other nodes may maintain the wrong value at the node where the SET was generated at first. In this manner, the fliped bit values in sequential element last, as a SEU until a new value is inputted to the element. Also, in the sequential elements, error rate of these radiation-induced errors may exceed the error rate in unprotected SRAM. Thus, a technique making the sequential element strong against the SEU is required.
RAZOR II which is a technique for handling a SEU in sequential elements has been developed. This technique includes a transition director circuit preventing a valid transition which may be detected as one error when a value is changed during a clock-to-Q delay of a latch. As a result, the circuit called as a transition director may detect only an invalid transition, and may not store the error.
SETTOFF which is another developed technique for handling a SEU in sequential elements has been developed. This technique may detect one error transmitted from input. Also, this technique may include a detection clock and transition detection circuit. And this technique may modify an output of a flip-flop by using an XOR logic. But this technique can modify an error only during a half of each clock period.
In addition to that, BISER which is another technique for handling a SEU in the sequential elements has been developed.
The prior arts handling the above-mentioned SEU of a sequential element may correct an error only for limited cases. Also, in the existing system, the reliability is limited because the sequential element hardware and the error-repairing hardware are implemented separately. Existing systems cannot repair an error occurred in the repairing hardware, because the repairing hardware are developed independently from the sequential element and only to access the error-repairing in the sequential element. Therefore, when an error occurs in the repairing hardware, the error processing system cannot properly repair the error occurred in the sequential element. Also, an potential error rate in the repairing hardware cannot be ignored because the repairing hardware requires many additional transistors.